In testing semiconductor IC devices by a semiconductor IC test system, such as a semiconductor memory, an IC device is placed on a test head of the IC test system. The IC test system supplies a test signal to the IC device under test wherein rising and falling edges of the test signal are controlled by a timing edge forming circuit. The IC test system has a large number of test signal paths (test channels) to supply test signals to corresponding input pins of the IC device under test.
An example of conventional timing edge forming circuits is shown in FIG. 4 wherein only one set of circuits is disclosed to be used for one test signal path of the IC test system. The timing edge forming circuit of FIG. 4 includes three identical timing generation circuits in parallel to form various timing edges of a test signal. The timing chart of FIG. 5 shows an example of timing edges for such a test signal which is further explained below.
One of the test procedures or test items in testing semiconductor IC devices by an IC test system is a test cycle in which device under test is tested by varying test cycles determined by a user. In such a test, a time interval for each test cycle is not fixed but has to be freely set through a test program. During this test cycle, a driver 51 provides a test signal, which is alternatively called a driver waveform, to the device under test. The driver waveform is wave-formatted to a desired waveform, such as a return to zero, a non-return to zero or an exclusive OR waveform by a wave formatter (not shown) before being applied to the device under test.
A relationship among the test cycle, the driver waveform and the timing edges is shown in FIG. 5. In each of the test cycles of FIG. 5, one or two driver waveforms for testing the IC device are produced having three timing edges which are delayed by t1, t2 and t3, respectively, from the starting edge of the test cycle. When generating one driver waveform, two timing edges, i,e., rising and falling edges, are necessary. Likewise, when generating two driver waveforms, four timing edges are necessary. In the case of FIG. 5, three driver waveforms are generated during two test cycles, a test cycle 1 and a test cycle 2. Therefore, three timing edges shown as timing edges t1, t2 and t3 are necessary for each test cycle to determine timings of the driver waveforms.
In general, one timing generation circuit is so structured to generate one timing edge in one test cycle. Thus, in a case where three timing edges are to be generated as in FIG. 5, three timing generation circuits are provided in a parallel form as shown in FIG. 4. The outputs of the timing generation circuits are combined by OR circuits 40.sub.1 and 40.sub.2, to provide set and reset signals to an RS flip-flop 50 for forming the driver waveforms generated by a driver 51.
In the following, description will be made as to the upper most timing generation circuit of FIG. 4. The timing generation circuit includes a timing generator 1, a format control gate 22.sub.1 in a format control 20 and a skew adjuster 30.sub.1 connected in series. A timing edge generated by this timing generation circuit provides either a set signal to the RS flip-flop 50 through the OR circuit 40.sub.1 or a reset signal to the RS flip-flop 50 through the OR circuit 40.sub.2. A pattern generator 5 generates address data which selects delay time data stored in the timing generator, a rate signal which is a basis of a test cycle, and a pattern data which shows a time difference between the test cycle and the rate signal. The rate signal, pattern data and the delay data define corresponding test cycles and timing edges of driver waveforms within the test cycles.
The timing generator 1 provides a timing edge ti having an delay time defined by the delay time data selected by the address data from the pattern generator 5 to the format control gate 22.sub.1. The timing generator 1 incudes a logic delay circuit 10, an enable gate 11 and a variable delay circuit 12. A reference clock signal CK is provided to the logic delay circuit 10 and the enable gate 11. The logic delay circuit 10 has a data memory M and a clock synchronous delay circuit in which a plurality of series connected flip-flops are driven by a high resolution clock signal CK. The clock synchronous delay circuit (not shown) generates an enable signal which is delayed from the rate signal provided by the pattern generator 5. The enable signal is arbitrarily delayed by an integer multiple of a time period of the clock signal in synchronism with the clock signal. The enable signal opens the enable gate 11 to pass therethrough in synchronism with the reference clock CK.
The frequency of the clock signal CK can be selected by a design choice such as 200 MHz which gives resolution of 5 ns since one period of the clock signal is 5 ns. However, the test cycle or the timing edges sometimes require higher resolution in time setting which is less than 5 ns, for example, 1 ns resolution is required. For example, time lengths of the test cycles may be 38 ns, 33 ns and 35 ns and delay times of the timing edges may be 14 ns, 14 ns and 12 ns, respectively, as shown in an example of FIG. 7.
In such a case, the variable delay circuit 12 is provided at the end of the enable gate 11 which provides an additional delay time which can be set by 1 ns increment, for example, under the control of high resolution delay data from the data memory M. The data memory M stores the high resolution delay data to control the variable delay circuit 12 when the test program requires timing resolution of less than the reference clock time period of 5 ns. The delay time based on the delay time signals from the data memory M can be changed in real time.
An example of circuit configuration for the variable delay circuit 12 is shown in FIG. 6. The example of FIG. 6 is configured by a plurality of IC gates each of which provides a delay time based on its signal propagation delay time. An input pulse signal is supplied to an input terminal 13 and delay time signals are supplied at an input terminal 14. The delay time signal is provide to AND gates 15.sub.1 and 15.sub.2 one of which is selectively opened. In case where the gate 15.sub.1 is selected, the input pulse signal is delayed by a delay circuit 16 which provides a delay time of 2ns and is supplied to an OR gate 17. When the gate 15.sub.2 is selected, the input pulse signal is supplied to the OR gate 17 without delay. In a similar manner, the input pulse signal is selectively coupled to circuits either with the delay or without the delay. Thus, the input pulse signal can freely acquire a ins delay time by a delay circuit 18 or a 500 picosecond (0.5 ns) delay time by a delay circuits 19. In the example of FIG. 6, the maximum of 4 ns delay time with 500 picosecond resolution is available.
In FIG. 4, a main format control 21 in the format control 20 receives the address data from the patten generator 5 and selects the format data therein to provide gate signals to the format control gates 22.sub.1, 22.sub.2 and 22.sub.3. In other words, an example of the main format control 21 is basically a memory which stores the format data to be supplied to the format control gates 22. In the format control gate 22, it is selected whether the enable signal from the timing generator 1 is to be used for forming a rising edge or a falling edge of the test signal. The selected enable signal is provided with an additional delay time by the skew adjuster 30 to adjust the skew between the plurality of signal paths and then supplied to the OR gates 40.sub.1 or 40.sub.2.
The skew within the context of this invention refers to differences of time in signal propagation delays among the plurality of signal paths relative to a reference time. In the example of FIG. 4, the timing edge forming circuit includes six signal paths toward the OR gates 40.sub.1 and 40.sub.2 to produce driver waveforms for one test channel. The time differences among the signal propagation delay in the signal paths from the reference time until the signals reaching the predetermined point such as the RS-flip-flop 50 is called a skew. The skew adjuster 30 adds delay times to each of the signal path so that all of the signal propagation times in the signal paths become the same. For example, the reference time is determined to be equal to the longest propagation time among the six signal paths.
Variable delay circuits 33 and 34 in the skew adjuster 30 have the same basic structure as used in the variable delay circuit 12 shown in FIG. 6. However, since the delay time required for adjusting the skew time in the variable delay circuits 33 and 34 is usually considerably larger than the delay time required for providing a high resolution delay time smaller than one cycle of the clock signal, the number of circuit components in the variable delay circuits 33 or 34 is considerably larger than that of the variable delay circuit 12 in the timing generator 1. Registers 31 and 32 are used to provide the delay time for the skew adjuster 33 and 34 since the delay time in the skew adjusters are fixed once adjusted.
FIG. 7 shows a timing chart of the operation of the timing edge forming circuit mentioned above. The test cycles of FIG. 7A and the delay times of the timing edges of FIG. 7E relative to the starting edges of the test cycles are determined by a user by means of a test program. In this example, the test cycle 1 is 38 ns and the delay time is 14 ns while the test cycle 2 is 33 ns and the corresponding delay time is 14 ns, which are written in the program. The frequency of the reference clock signal CK of FIG. 7B is 200 MHz and thus the time period thereof is 5 ns.
The rate signal which is synchronous with the reference clock CK as shown in FIG. 7C and the pattern data (PADAT) of FIG. 7D which shows time differences between the test cycles and the rate signals are provided to the logic delay circuit 10 from the pattern generator 5. By the address data from the pattern generator 5, the timing generator produces the delay data shown in FIG. 7E indicating the delay times of the timing edges of the driver waveforms (test signals) within the test cycles. Both the rate signal which is synchronous with the reference clock period 5 ns and the pattern data (PADAT) produce the above noted time length of each test cycle.
In the test cycle 1, the example of the delay time of the timing edge is 14 ns as shown in FIG. 7E. Thus, the logic delay circuit 10 sends an enable signal (FIG. 7F) having 5 ns pulse width and ions after the start of the test cycle 1 to the enable gate 11. The enable signal is synchronized with the clock signal CK in the enable gate 11 so that the output of the enable gate 11 which is a gated clock signal is produced after ions from the start of the test cycle 1. The variable delay circuit 12 provides a delay time of 4 ns to form a 14 ns timing edge as shown in FIG. 7I. The skew adjuster 30 adds a predetermined time to the signal from the from the variable delay circuit 12 via the format control gate 20 to compensate the propagation delay time differences among the other signal paths. In the example of FIG. 7J, a delay time of ions is automatically added to the gated clock signal from the variable delay circuit 12 to adjust the skew. The output of the skew adjuster 30 is supplied to the OR circuits 40.sub.1 or 40.sub.2.
The timing edges in the conventional semiconductor IC test system are formed as described above. As shown in FIG. 4, three identical timing circuits are used in parallel to generate timing edges, each circuit of which generates either a rising edge or a falling edge. Namely, the timing edges are generated by the timing generators 1-3, the format control gates 22, the skew adjusters 30 and applied to the RS flip-flop 50 via the OR gates through six signal paths. In FIG. 4, the six signal paths extend from the variable delay circuits 33 and 34 to the OR gates 40.
The timing edge forming circuit for producing high resolution timing edges are important to determine the ability of the semiconductor IC test system. However, the overall length of the signal paths, such as signal paths from the skew adjusters 30 to the OR gates 40, limit the possible resolution in the timing edges since the signal propagation times in the signal paths will change with environmental variations such as temperature changes.
As noted above, since the delay time required for adjusting the skew time in the variable delay circuits 33 and 34 is considerably larger than the delay time required for providing the high resolution delay time which is smaller than one cycle of the clock signal, the number of circuit components and the signal path length in the variable delay circuits 33 or 34 become considerably large. In addition, the variable delay circuits 33 and 34 produce delay times based on the signal propagation delay time in each IC gate which is not very stable since such propagation delay time is an analog time. Thus, the conventional timing edge forming circuit has a problem that it is difficult to produce high resolution timing edges.
Further, when the signal path is long, the timing edges are more affected by jitter in the signal paths, which also lowers the accuracy of the timing edges. Therefore, there is a need to reduce the overall length of the signal paths extending from the timing generator to the format control gate, the skew adjuster and the OR gate and to the RS flip-flop. It is also expected that shortening the signal path length will reduce the uncertainty of timing resolution involved in designing the timing circuits, which will ease a designing process in this kind of timing circuit.
Furthermore, the conventional timing edge forming circuit requires a large number of circuit components such as in the skew adjusters for establishing high resolution, which results in high cost. In addition, the conventional timing edge forming circuit made it difficult to simplify the design and adjustment of the circuits since a large number of analog hardware components are used which need special attention in terms of timing resolution.